Semiconductor devices are fabricated step-by-step, beginning with a silicon wafer (substrate), implanting various ions, depositing insulating and conductive layers. Some of these layers are subsequently etched by using a patterned photoresist as a mask to create various circuit structures; wherein these pattern transferring processes substantially include a photolithography process, transferring a pattern of a mask to a photoresist layer overlying the silicon wafer, and then a dry etching process, transferring a pattern of the photoresist layer to these insulating or conductive layers by selectively removing unmasked area thereof. However, it is often difficult to obtain a faithful pattern on the photoresist layer overlying highly reflective layers during the photolithography process because the amount of exposing light that the layers reflect can partially expose some of the photoresist. The major highly reflective layers are metal layers such as aluminum or gold. This problem becomes more significant as the patterns become finer because the amount of reflected light has a greater relative effect on exposing a thin line, which casts a narrow shadow, than a thick line, which casts a wide shadow. Therefore, It is needed to have an Antireflection Coating (hereinafter referred as ARC) layer on top of the highly reflective layers to improve the resolution of the photoresist pattern and subsequent precision of the pattern in the reflective layers. Most material of the ARC layer is TiN.
Since the silicon wafer has finished most processes of whole integrated circuit wherein even more includes a multilevel metalliztion structure before forming the ARC layer, its surface topology is such uneven that weak points of the followed formed ARC layer often occur at recess regions. When the silicon wafer is immersed in an acidic solution, for example, a developer or an alkalescent solution, these solutions will diffuse from these weak points of the ARC layer into the underlying highly reflective layer such as metal layer, as shown in FIG. 1. After forming a first metal pattern 20 atop a silicon wafer (substrate) 10, an interlevel dielectric layer 30 such as oxide, a second metal layer 40 such as aluminum to be formed a second metal pattern in following processes, and a thickness of 300-500 angstroms of ARC layer 50 such as TiN are formed in this sequence, shown in FIG. 1. As aforesaid, if the silicon wafer is immersed in an acidic or alkalescent solution, these solutions will diffuse from weak points A (generally at recess regions) and that will result in a Galvanic cell effect. The Galvanic cell effect is substantially an electrochemical battery and comprises the second metal layer 40 as an anode, the ARC layer as a cathode, and the acidic or alkalescent solution as electrolyte, thereby the second metal layer 40 electrolyzed and etched to form voids at these recess regions, as shown in a double-declined line area of FIG. 1, which further make the second metal layer 40 lose its integrity, increase its resitivity, and even more form an open circuit, thus considerably lowering reliability of product.
Except that said recess regions of surface topology of the silicon wafer may form weak points, it is inevitable that some particles, coming from a chamber and co-deposited on the silicon wafer during a sputter depositing process of ARC material of TiN, also may form these weak points and deteriorate quality of the ARC layer. For the time being, there is no other method to monitor quality of the ARC layer except by an inference from back-end test of electric parameters of the silicon wafer and thus yield of product will be lowered because a timely reworking process can""t be applied to the bad quality of the ARC layer. Therefore, it is needed to propose a monitor method for quality of the ARC layer allowing for obtaining a fast and accurate response to remind operators applying a timely reworking process, thereby raising yield of product.
Therefore, an object of the invention is to provide a monitor method for quality of the ARC layer allowing for obtaining a fast and accurate response to remind operators applying a timely reworking process, thereby raising yield of product.
It is another object of the invention to provide an in-line monitor method for quality of the ARC layer because of its sample wafer prepared from a production line, i.e. a developing Process.
By immersing a silicon wafer comprising an ARC layer into an acidic (such as developing solution) or alkalescent solution for about 200-300 seconds, according to the present invention, the weak points of the metal ARC layer which occur as voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then counting the number of defects by a wafer defect detector such as a KLA instrument so that the quality of the metal ARC layer can be monitored by this defect number. Since the silicon wafer used as a sample for the wafer defect detector comes from a production line, i.e. a developing process, rather than from other additional processing, this method allows for fast and accurately monitoring quality of the metal ARC layer.